1. Field of the Invention
The present invention pertains to computer systems and computer system buses. More particularly, this invention relates to controlling the ordering of data transfers on a bus in a computer system.
2. Background
Modern computer systems typically have multiple agents coupled together via a system bus. Typically, the agents are integrated circuit chips with multiple pins coupling each agent to the bus. These agents may include, for example, processors, memory devices, mass storage devices, etc. Data is frequently transferred between these different agents on the bus. By way of example, data is often transferred from either a memory device or a bus bridge to a processor. In order for the computer system to operate properly, these agents should be able to effectively transfer data between each other via the bus.
The bus includes multiple data lines, each of which is capable of transferring one bit of data. The number of clock cycles that a bit of data is required to be on the data line in order to be received by another agent is dependent on the bus protocol, but typically ranges from one to a few clock cycles. The total number of data lines in a bus is referred to as the data bus width.
Modern computer systems also typically include one or more cache memories for storing data and/or instructions. A cache memory is typically smaller and faster than the main computer system memory and is used to temporarily store data for an agent(s). Cache memories store data in quantities referred to as cache lines, which are typically larger than the data bus width and also typically larger than the data path width within the processor(s) of the system. For example, a computer system may have a data bus width of 64 bits, but a cache line size of 256 bits.
Often times, when a requesting agent needs a portion of data from another agent on the bus, the requesting agent sends a request over the bus for the cache line which includes the needed portion. Thus, situations can arise where, for example, a request for data by a requesting agent (e.g., a processor) from a second agent (e.g., a memory device) can be a request for an amount of data, such as a cache line, which is greater than the data bus width. Therefore, the requested cache line is broken into multiple portions, each having the same number of bits as the data bus width, and these multiple portions are transferred to the requesting agent over a period of multiple clock cycles. By way of another example, data requested by a requesting agent (e.g., a processor) may be stored in a second agent's cache memory, and the cache line, which is greater than the data bus width, is returned to the requesting agent or another agent on the bus (e.g., a memory controller) from the second agent in multiple portions. However, in both examples these multiple portions are typically transferred in order from least significant to most significant byte of the cache line, without regard for which byte or bytes are actually needed by the requesting agent. Therefore, given that the second agent is transferring the entire cache line over multiple clock cycles, it would be beneficial to provide a mechanism for the particular portion of data which is needed by the requesting agent to be provided to that agent prior to the remaining portions.
As will be described in more detail below, the present invention provides a method and apparatus for ordering data transfers on a bus to achieve these and other desired results which will be apparent to those skilled in the art from the description that follows.